1. Field of the Invention
The present invention relates to a semiconductor device including an element, for example, a MOS transistor which has a so-called buried gate electrode, and to a manufacturing method thereof.
2. Description of the Related Art
With recent development in miniaturization and integration of semiconductor devices, techniques for reducing the resistance of electrodes and a variety of wires have been considered for increasingly miniaturized and highly integrated semiconductor devices. One of promising techniques is a so-called salicide method which forms a silicide layer on each of a gate electrode and source/drain electrodes of a transistor. This method forms a refractory metal film such as a Ti film or the like overlying a gate electrode and a source/drain structure, and reacts the refractory metal film with the gate electrode and the source/drain electrodes by a heat treatment to form a silicide layer.
On the other hand, a buried gate transistor has been proposed for reducing a difference of level or height in a semiconductor device to achieve further miniaturization and integration. Specifically, the buried gate transistor is fabricated by forming a strip-like groove in a semiconductor substrate, and filling a conductive material into this groove to form a gate electrode.
In the buried gate transistor having a salicide structure as mentioned above, if source/drain electrodes are formed with a small junction depth, for example, as is the case of an LDD structure, silicide layers are formed to intrude into the semiconductor substrate so that the silicide layers extend deeper than the junction depth of the source/drain electrodes, thus causing a fear of short-circuiting with the semiconductor substrate.
JP-A-2-46775 discloses a semiconductor device which has a silicide layer formed on a portion of the surface of a buried gate electrode as a contact with an upper electrode.
Although, according to JP-A-2-46775, the disclosed technique does eliminate the problem of the silicide layer formed deeper than the junction depth of the source/drain electrodes, another problem arises as follows. In a buried gate transistor, an insulating film for isolating a gate electrode from a semiconductor substrate is formed by thermal oxidization on the inner wall of a groove together with a gate insulating film. Although this insulating film has substantially the same thickness as the gate insulating film, reliable separation of a silicide layer on the gate electrode from a silicide layer on source/drain electrodes is difficult for the insulating film of such a thickness to achieve. In this case, therefore, the resultant transistor will inevitably suffer from significant degradation in characteristics.
JP-A-7-30104 in turn discloses a semiconductor device which has a side-wall insulating film formed inside of a groove for forming a gate electrode therein so as to physically and electrically separate a silicide layer on the gate electrode and silicide layers on source/drain electrodes by this side-wall insulating film in a silicide forming step.
This side-wall insulating film, however, does not cover a side wall of the gate electrode, so that the gate electrode is located in a close proximity to the source/drain electrodes only with an intervening gate insulating film, thus incurring a danger of leading to possible short-circuiting therebetween and an increase in parasitic capacitance.
Further, JP-A-8-32063 discloses a semiconductor device which has a silicon oxide film formed on the bottom surface of a groove for forming a gate electrode therein, and a titanium film deposited thereon, with the silicon oxide film and the titanium film being thermally treated to form a titanium silicide film on the interface therebetween.
In this semiconductor device, however, no silicide films are formed on source/drain electrodes. Neither is there formed a side-wall insulating film for covering the side wall of the gate electrode.